Multi Parametric Design Space Exploration (DSE) for optimal micro-architecture synthesis is an extremely complex yet crucial stage in embedded systems development. Often it is very time complex to find the best suitable configuration to map the inherently contradictory performance parameters into systems silicon real estate. Owing to its exponentially exploding design space and multi way combinatorial mapping, DSE has proven to be notoriously hard and intractable for VLSI CAD tools. The presented work introduces a highly scalable and generalized analytical approach to identify the best configuration of systems architecture while maintaining prime accuracy resolution. This DSE approach coupled with Stability in Competition principles has been applied to a number of well known benchmark High Level Synthesis (HLS) applications, with an impressive 71.80% aggregate speedup and results being more pronounced for larger design space HLS applications.