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10-bit double-segmented thermometer-coded current steering DAC

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posted on 2021-05-23, 13:22 authored by Ali Sepehr

This design describes a 10-Bit, 200-MHz Double-Segmented Thermometer-Codes Current Steering digital to analog converter. A current-sterring DAC is a power-efficient architecture, and also highly suitable for high-speed operation, but suffers from poor linearity characteristics. The problem can be prevented with a thermometer-coded technique. The DAC includes two-stage folded-cascode Op-Amp. The 10-bit DAC architecture consists of a 4 least significant bits entering to 4-bit thermometer-coded decoder and 6 most significant bits enterin 6-bit thermometer-coded decoder, driving 960 equally weighted current sources. The double-segmented architecture allows the designed DAC to reduce not only the complexity of decoding logic, but also a number of current sources. The differential non-linearity (DNL) and integral non-linearity (INL) are 0,15 and 0.3 of least significant bits, respectively. Although designed to operate well about 1 GHz, Op-Amp limited the speed of the device to a 200-MHz clock rate. Low linearity errors (DNL and INL), 200-MHz conversion rate, low glitch energy, and 1.8V from a single voltage supply by using 0.18 um CMOS technology makes this DAC suitable for graphic systems.

History

Language

eng

Degree

  • Master of Applied Science

Program

  • Electrical and Computer Engineering

Granting Institution

Ryerson University

LAC Thesis Type

  • Thesis

Thesis Advisor

Kaamran Raahemifar

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    Electrical and Computer Engineering (Theses)

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