The hardware acceleration of the wavelet transform for real-time systems has become an essential research field. In the first part of the thesis, an efficient architecture that performs both forward and inverse lifting-based discrete wavelet transform is proposed. The proposed architecture reduces the hardware requirement by exploiting the redundancy in the arithmetic operation involved in DWT computation. The proposed architecture consists of predict module, update module, address generation module, control unit and a set of registers to establish data communication between predict and update modules. The symmetrical extension of images at the boundary to reduce distorted images has been incorporated in our proposed for both (5,3) wavelet and (9,7) wavelet. Best-basis algorithm that is designed for signal compression and de-noising uses WPT to select the best-basis node for a given additive cost function. In the second part of the thesis, we propose wavelet architecture to perform WPT decomposition. A new algorithm to implement the natural logarithm function using Maclaurin series is proposed to implement the cost function used for best-basis algorithm. These architectures have been described in VHDL at the RTL level and simulated successfully using ModelSim simulation environment. These architectures are implemented in Virex ll Pro FPGA series of Xilinx.