The large arithmetic-intensive applications increasingly implemented on field-programmable gate arrays (FPGAs) challenge FPGA architects to design FPGAs that can efficiently transport large amount of multi-bit wide signals in the data-path circuits of these applications. In this work, we investigate the area efficiency of two FPGA multi-bit aware routing architectures - the sparse and the enhanced sparse architectures, and compare them with the conventional and the configuration memory sharing architectures. We found that the sparse and enhanced sparse architectures are 6-10% more efficient than the conventional architecture. Our data also show that while the configuration memory sharing architecture can achieve the highest level of theoretical area savings for multi-bit transportation, it performs poorly for circuits with 50% or less multi-bit signals. These results suggest that FPGA architects should look beyond conventional architectures in order to create more efficient routing architectures for modern FPGAs.