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Concurrent Transaction Logic with Priority and Timing Constraints
Title
Concurrent Transaction Logic with Priority and Timing Constraints
Date
2004
Author(s)
Ge, Jiwen (Author), Santos, Marcus (Thesis advisor), Ryerson University (Degree granting institution)
Subject(s)
Computer programming, Logic
Program
Electrical and Computer Engineering
Mereotopology for product modeling
Title
Mereotopology for product modeling
Date
2002
Author(s)
Salustri, Filippo A. (Author)
Subject(s)
Mereotopology, Logic, Design, Engineering
DOI
10.1504/JDR.2002.009816